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| FEDD5118160F-01 1 Semiconductor MSM5118160F 1,048,576-Word x 16-Bit DYNAMIC RAM : FAST PAGE MODE TYPE This version: June. 2000 Previous version : DESCRIPTION The MSM5118160F is a 1,048,576-word x 16-bit dynamic RAM fabricated in Oki's silicon-gate CMOS technology. The MSM5118160F achieves high integration, high-speed operation, and low-power consumption because Oki manufactures the device in a quadruple-layer polysilicon/double-layer metal CMOS process. The MSM5118160F is available in a 42-pin plastic SOJ or 50/44-pin plastic TSOP. FEATURES * 1,048,576-word x 16-bit configuration * Single 5V power supply, 10% tolerance * Input : TTL compatible, low input capacitance * Output : TTL compatible, 3-state * Refresh : 1024 cycles/16ms * Fast page mode, read modify write capability * CAS before RAS refresh, hidden refresh, RAS-only refresh capability * Packages (SOJ42-P-400-1.27) 42-pin 400mil plastic SOJ (Product : MSM5118160F-xxJS) 50/44-pin 400mil plastic TSOP (TSOPII50/44-P-400-0.80-K) (Product : MSM5118160F-xxTS-K) xx indicates speed rank. PRODUCT FAMILY Access Time (Max.) Family tRAC 50ns 60ns 70ns tAA 25ns 30ns 35ns tCAC 13ns 15ns 20ns tOEA 13ns 15ns 20ns Cycle Time (Min.) 90ns 110ns 130ns Power Dissipation Operating (Max.) 743mW 688mW 633mW Standby (Max.) 5.5mW MSM5118160F 1/15 FEDD5118160F-01 1 Semiconductor MSM5118160F PIN CONFIGURATION (TOP VIEW) VCC 1 DQ1 2 DQ2 3 DQ3 4 DQ4 5 VCC 6 DQ5 7 DQ6 8 DQ7 9 DQ8 10 NC 11 NC 12 WE 13 RAS 14 NC 15 NC 16 A0 17 A1 18 A2 19 A3 20 VCC 21 42-Pin Plastic SOJ 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 VSS DQ16 DQ15 DQ14 DQ13 VSS DQ12 DQ11 DQ10 DQ9 NC LCAS UCAS OE A9 A8 A7 A6 A5 A4 VSS VCC 1 DQ1 2 DQ2 3 DQ3 4 DQ4 5 VCC 6 DQ5 7 DQ6 8 DQ7 9 DQ8 10 NC 11 50 49 48 47 46 45 44 43 42 41 40 VSS DQ16 DQ15 DQ14 DQ13 VSS DQ12 DQ11 DQ10 DQ9 NC NC 15 NC 16 WE 17 RAS 18 NC 19 NC 20 A0 21 A1 22 A2 23 A3 24 VCC 25 36 35 34 33 32 31 30 29 28 27 26 NC LCAS UCAS OE A9 A8 A7 A6 A5 A4 VSS 50/44-Pin Plastic TSOP (K Type) Pin Name A0-A9 RAS LCAS UCAS DQ1-DQ16 OE WE VCC VSS NC Function Address Input Row Address Strobe Lower Byte Column Address Strobe Upper Byte Column Address Strobe Data Input/Data Output Output Enable Write Enable Power Supply (5V) Ground (0V) No Connection Note : The same power supply voltage must be provided to every VCC pin, and the same GND voltage level must be provided to every VSS pin. 2/15 FEDD5118160F-01 1 Semiconductor MSM5118160F BLOCK DIAGRAM WE RAS LCAS UCAS Column Address Buffers Internal Address Counter Timing Generator I/O Controller I/O Controller 10 10 Column Decoders 8 Output Buffers 8 DQ1-DQ8 8 I/O Selector Input Buffers 8 OE A0-A9 Refresh Control Clock Sense Amplifiers 16 16 Input Buffers 8 10 Row Address Buffers 10 Row Decoders Word Drivers Memory Cells 8 8 DQ9-DQ16 Output Buffers 8 VCC On Chip VBB Generator On Chip IVCC Generator VSS FUNCTION TABLE Input Pin RAS H L L L L L L L L LCAS * H L H L L H L L UCAS * H H L L H L L L WE * * H H H L L L H OE * * L L L H H H H DQ Pin Function Mode DQ1-DQ8 High-Z High-Z DOUT High-Z DOUT DIN Don't Care DIN High-Z DQ9-DQ16 High-Z High-Z High-Z DOUT DOUT Don't Care DIN DIN High-Z Standby Refresh Lower Byte Read Upper Byte Read Word Read Lower Byte Write Upper Byte Write Word Write * : "H" or "L" 3/15 FEDD5118160F-01 1 Semiconductor MSM5118160F ELECTRICAL CHARACTERISTICS ABSOLUTE MAXIMUM RATINGS Parameter Voltage on Any Pin Relative to VSS Voltage VCC Supply relative to VSS Short Circuit Output Current Power Dissipation Operating Temperature Storage Temperature Symbol VIN, VOUT VCC IOS PD* Topr Tstg Value -0.5 to VCC+ 0.5 -0.5 to 7 50 1 0 to 70 -55 to 150 Unit V V mA W C C *: Ta = 25C RECOMMENDED OPERATING CONDITIONS (Ta = 0 to 70C) Parameter Power Supply Voltage Input High Voltage Input Low Voltage Symbol VCC VSS VIH VIL Min. 4.5 0 2.4 - 0.5*2 Typ. 5.0 0 Max. 5.5 0 VCC + 0.5 0.8 *1 Unit V V V V Notes: *1. The input voltage is VCC + 2.0V when the pulse width is less than 20ns (the pulse width is with respect to the point at which VCC is applied). *2. The input voltage is VSS - 2.0V when the pulse width is less than 20ns (the pulse width respect to the point at which VSS is applied). PIN CAPACITANCE (Vcc = 5V 10%, Ta = 25C, f = 1 MHz) Parameter Input Capacitance (A0 - A9) Input Capacitance (RAS, LCAS, UCAS, WE, OE) Output Capacitance (DQ1 - DQ16) Symbol CIN1 CIN2 CI/O Min. -- -- -- Typ. -- -- -- Min. 5 7 7 Unit pF pF pF 4/15 FEDD5118160F-01 1 Semiconductor MSM5118160F DC CHARACTERISTICS (VCC = 5V 10%, Ta = 0 to 70C) MSM5118160 F-50 Min. Output High Voltage Output Low Voltage Input Leakage Current Output Leakage Current Average Power Supply Current (Operating) Power Supply Current (Standby) Average Power Supply Current (RAS-only Refresh) Power Supply Current (Standby) Average Power Supply Current (CAS before RAS Refresh) Average Power Supply Current (Fast Page Mode) VOH VOL IOH = -5.0mA IOL = 4.2mA 0V VI 6.5V; ILI All other pins not under test = 0V DQ disable 0V VO VCC RAS, CAS cycling, tRC = Min. RAS, CAS = VIH ICC2 RAS, CAS VCC - 0.2V RAS cycling, ICC3 CAS = VIH, tRC = Min. RAS = VIH, ICC5 CAS = VIL, DQ = enable RAS = cycling, CAS before RAS RAS = VIL, ICC7 CAS cycling, tPC = Min. 120 110 100 mA 1,3 5 5 5 mA 1 135 125 115 mA 1,2 - 10 10 - 10 10 - 10 10 A 2.4 0 Max. VCC 0.4 MSM5118160 F-60 Min. 2.4 0 Max. VCC 0.4 MSM5118160 F-70 Unit Note Min. 2.4 0 Max. VCC 0.4 V V Parameter Symbol Condition ILO - 10 10 - 10 10 - 10 10 A ICC1 135 125 115 mA 1,2 2 1 2 1 2 mA 1 1 ICC6 135 125 115 mA 1,2 Notes: 1. ICC Max. is specified as ICC for output open condition. 2. The address can be changed once or less while RAS = VIL. 3. The address can be changed once or less while CAS = VIH. 4. VCC - 0.2V VIH VCC + 0.5V, - 0.5V VIL 0.2V 5/15 FEDD5118160F-01 1 Semiconductor MSM5118160F AC CHARACTERISTICS (1/2) (VCC = 5V 10%, Ta = 0 to 70C) Note1,2,3 Parameter Symbol MSM5118160 F-50 Min. Random Read or Write Cycle Time Read Modify Write Cycle Time Fast Page Mode Cycle Time tRC tRWC tPC 90 131 35 76 0 0 0 1 30 50 50 13 13 7 13 50 5 30 17 12 0 Max. 50 13 25 30 13 13 13 50 16 10,000 100,000 10,000 37 25 MSM5118160 F-60 Min. 110 155 40 85 0 0 0 1 40 60 60 15 15 10 15 60 5 35 20 15 0 Max. 60 15 30 35 15 15 15 50 16 10,000 100,000 10,000 45 30 MSM5118160 F-70 Min. 130 185 45 100 0 0 0 1 50 70 70 20 20 10 20 70 5 40 20 15 0 Max. 70 20 35 40 20 20 20 50 16 10,000 ns ns ns ns ns ns ns ns ns ns ns ns ns ms ns ns 4, 5, 6 4, 5 4, 6 4, 12 4 4 7 7 3 Unit Note Fast Page Mode Read Modify Write tPRWC Cycle Time Access Time from RAS Access Time from CAS Access Time from Column Address Access Time from CAS Precharge Access Time from OE Output Low Impedance Time from CAS CAS to Data Output Buffer Turnoff Delay Time OE to Data Output Buffer Turn-off Delay Time Transition Time Refresh Period RAS Precharge Time RAS Pulse Width tRAC tCAC tAA tCPA tOEA tCLZ tOFF tOEZ tT tREF tRP tRAS RAS Pulse Width (Fast Page Mode) tRASP RAS Hold Time RAS Hold Time referenced to OE CAS Precharge Time (Fast Page Mode) CAS Pulse Width CAS Hold Time CAS to RAS Precharge Time tRSH tROH tCP tCAS tCSH tCRP 100,000 ns 10,000 50 35 ns ns ns ns ns ns ns ns ns ns 12 12 5 6 14 RAS Hold Time from CAS Precharge tRHCP RAS to CAS Delay Time RAS to Column Address Delay Time Row Address Set-up Time tRCD tRAD tASR 6/15 FEDD5118160F-01 1 Semiconductor MSM5118160F AC CHARACTERISTICS (2/2) (VCC = 5V 10%, Ta = 0 to 70C) Note1,2,3 Parameter Symbol MSM5118160 F-50 Min. Row Address Hold Time Column Address Set-up Time Column Address Hold Time Column Address to RAS Lead Time Read Command Set-up Time Read Command Hold Time Read Command Hold Time referenced to RAS Write Command Set-up Time Write Command Hold Time Write Command Pulse Width OE Command Hold Time Write Command to RAS Lead Time Write Command to CAS Lead Time Data-in Set-up Time Data-in Hold Time OE to Data-in Delay Time CAS to WE Delay Time Column Address to WE Delay Time RAS to WE Delay Time CAS Precharge WE Delay Time CAS Active Delay Time from RAS Precharge RAS to CAS Set-up Time (CAS before RAS) RAS to CAS Hold Time (CAS before RAS) tRAH tASC tCAH tRAL tRCS tRCH tRRH tWCS tWCH tWP tOEH tRWL tCWL tDS tDH tOED tCWD tAWD tRWD tCPWD tRPC tCSR tCHR 7 0 7 25 0 0 0 0 7 7 13 13 13 0 7 13 36 48 73 53 5 5 10 Max. MSM5118160 F-60 Min. 10 0 10 30 0 0 0 0 10 10 15 15 15 0 10 15 40 55 85 60 5 5 10 Max. MSM5118160 F-70 Min. 10 0 15 35 0 0 0 0 15 10 20 20 20 0 15 20 50 65 100 70 5 5 10 Max. ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 9 9 9 9 11 11 12 13 10, 11 10, 11 11 8, 11 8 9, 11 11 11 11 Unit Note 7/15 FEDD5118160F-01 1 Semiconductor MSM5118160F Notes: 1. A start-up delay of 200s is required after power-up, followed by a minimum of eight initialization cycles (RAS-only refresh or CAS before RAS refresh) before proper device operation is achieved. 2. The AC characteristics assume tT = 5ns. 3. VIH (Min.) and VIL (Max.) are reference levels for measuring input timing signals. Transition times (tT) are measured between VIH and VIL. 4. -50 is measured with a load circuit equivalent to 2 TTL load and 50pF, and -60/-70 is measured with a load circuit equivalent to 2 TTL load and 100pF. 5. Operation within the tRCD (Max.) limit ensures that tRAC (Max.) can be met. tRCD (Max.) is specified as a reference point only. If tRCD is greater than the specified tRCD (Max.) limit, then the access time is controlled by tCAC. 6. Operation within the tRAD (Max.) limit ensures that tRAC (Max.) can be met. tRAD (Max.) is specified as a reference point only. If tRAD is greater than the specified tRAD (Max.) limit, then the access time is controlled by tAA. 7. tOFF (Max.) and tOEZ (Max.) define the time at which the output achieved the open circuit condition and are not referenced to output voltage levels. 8. tRCH or tRRH must be satisfied for a read cycle. 9. tWCS, tCWD, tRWD, tAWD and tCPWD are not restrictive operating parameters. They are included in the data sheet as electrical characteristics only. If tWCS tWCS (Min.), then the cycle is an early write cycle and the data out will remain open circuit (high impedance) throughout the entire cycle. If tCWD tCWD (Min.), tRWD tRWD(Min.), tAWD tAWD (Min.) and tCPWD tCPWD (Min.), then the cycle is a read modify write cycle and data out will contain data read from the selected cell; if neither of the above sets of conditions is satisfied, then the condition of the data out (at access time) is indeterminate. 10. These parameters are referenced to the UCAS and LCAS, leading edges in an early write cycle, and to the WE leading edge in an OE control write cycle, or a read modify write cycle. 11. These parameters are determined by the falling edge of either UCAS or LCAS, whichever is earlier. 12. These parameters are determined by the rising edge of either UCAS or LCAS, whichever is later. 13. tCWL should be satisfied by both UCAS and LCAS. 14. tCP is determined by the time both UCAS and LCAS are high. 8/15 FEDD5118160F-01 1 Semiconductor MSM5118160F TIMING CHART Read Cycle RAS VIH VIL tCRP CAS VIH VIL tASR Address VIH VIL VIH VIL VIH VIL tRAC DQ VOH VOL tCLZ Open Valid Data-out "H" or "L" tAA tROH tOEA tCAC tOEZ tRCH tRAD tRAL tRAH tASC Column tRCS tRRH tCAH tRCD tCSH tRSH tCAS tCRP tRC tRAS tRP Row WE OE tOFF Write Cycle (Early Write) VIH VIL tCRP CAS VIH VIL tASR Address VIH VIL tRAD tRAL tRAH tASC tCAH Column tCWL tWCS tWP tWCH tRCD tRC tRAS tRP tCSH tRSH tCAS tCRP RAS Row WE VIH VIL VIH VIL VIH VIL tRWL OE tDS tDH Open "H" or "L" DQ Valid Data-in 9/15 FEDD5118160F-01 1 Semiconductor MSM5118160F Read Modify Write Cycle tRWC RAS VIH VIL tCRP CAS VIH VIL tASR Address VIH VIL tRAD tRAH tASC Colum tRCS tRWD WE VIH VIL VIH VIL tRAC DQ VI/OH VI/OL tCLZ Valid Data-out tRAS tRP tCSH tRCD tRSH tCAS tCWL tRWL tCRP tCAH Row tCWD tWP tAWD tAA tOEA tOED tCAC tOEZ tDS Valid Data-in tOEH OE tDH "H" or "L" 10/15 FEDD5118160F-01 1 Semiconductor MSM5118160F Fast Page Mode Write Cycle tRASP RAS VIH VIL tCRP CAS VIH VIL tASR Address VIH VIL VIH VIL VIH VIL tRAC tCAC DQ VOH VOL tCLZ tCPA tOFF tOEZ Valid Data-out tRP tPC tRHCP tCP tCAS tRSH tCAS tRAL tRCD tCAS tRAD tCSH tRAH tASC tCAH tCP tCRP tASC tCAH tASC Column tRCH tAA tRCS tCAH Row tRCS Column tRCH tAA tOEA Column tRCS tAA tOEA tRCH WE tOEA tCPA tRRH OE tCAC tCLZ tOFF tOEZ Valid Data-out tCAC tOEZ tCLZ Valid Data-out tOFF "H" or "L" Fast Page Mode Write Cycle (Early Write) tRASP RAS VIH VIL VIH VIL tASR Address VIH VIL Row tRAD tRAH tASC tCSH tCAH tASC tCAH tASC tRAL tCAH Column tRWL tCWL tWCS WE VIH VIL tDS DQ VIH VIL Valid * Data-in tCWL tRP tPC tRHPC tCP tCAS tRSH tCAS tCRP tCRP tRCD tCAS tCP CAS Column Column tCWL tWCS tWCH tWP tWCS tWCH tWP tWP tWCH tDH tDS Valid * Data-in tDH tDS Valid * Data-in tDH Note: OE = "H" or "L" "H" or "L" 11/15 FEDD5118160F-01 1 Semiconductor MSM5118160F Fast Page Mode Read Modify Write Cycle tRASP RAS VIH VIL VIH VIL tRAH tASR Address VIH VIL Row tCSH tRCD tRAD tASC Column tPRWC tCAS tCP tCAS tCAH tCAH tCWL tASC tCWL Column Column tRSH tCP tCAS tCAH tASC tCRP tRP CAS tRAL tRCS WE VIH VIL tRAC tAA tPWD tCWD tAWD tWP tDH tOEA tDS tOED tCAC tOEZ Out tRCS tCPWD tRCS tCPWD tCWL tRWL tCWD tAWD tCPA tAA tOEA tOED tOEZ tCAC In tCLZ Out tDS In tCLZ tCAC tWP tDH tAA tCWD tAWD tWP tROH tCPA tOEA tOED tOEZ tDH tDS OE VIH VIL VI/OH VI/OL tCLZ DQ Out In Note: In = Valid Data-in, Out = Valid Data-out "H" or "L" RAS-only Refresh Cycle RAS tRC RAS VIH VIL tCRP CAS VIH VIL VIH VIL VOH VOL tASR tRAH Row tOFF Open Note: WE, OE = "H" or "L" "H" or "L" tRPC tRAS tRP Address DQ 12/15 FEDD5118160F-01 1 Semiconductor MSM5118160F CAS before RAS Refresh Cycle tRP RAS VIH VIL tRPC tCP tRAS tRP tCSR tCHR tRPC tRC CAS VIH VIL tOFF VOH VOL DQ Open Note: WE, OE, Address = "H" or "L" "H" or "L" Hidden Refresh Read Cycle tRC RAS VIH VIL VIH VIL tASR Address VIH VIL VIH VIL tAA tROH OE VIH VIL VOH VOL tRAC tCLZ Open Valid Data-out "H" or "L" tOEA tOEZ tOFF tCRP tRCD tRAD tRAH Row tRCS WE tASC Column tCAC tRAL tRRH tCAH tRAS tRSH tRP tCHR CAS tRC tRAS tRP DQ 13/15 FEDD5118160F-01 1 Semiconductor MSM5118160F Hidden Refresh Write Cycle tRC RAS VIH VIL VIH VIL tASR Address VIH VIL VIH VIL VIH VIL VIH VIL tDS tDH tWP tRAH Row tWCS WE tRAD tRAL tASC Column tWCH tCAH tCRP tRCD tRAS tRSH tRP tCHR tRAS tRP tRC CAS OE DQ Valid Data-in "H" or "L" 14/15 FEDD5118160F-01 1 Semiconductor MSM5118160F NOTICE 1. The information contained herein can change without notice owing to product and/or technical improvements. Before using the product, please make sure that the information being referred to is up-to-date. 2. The outline of action and examples for application circuits described herein have been chosen as an explanation for the standard action and performance of the product. When planning to use the product, please ensure that the external conditions are reflected in the actual circuit, assembly, and program designs. 3. When designing your product, please use our product below the specified maximum ratings and within the specified operating ranges including, but not limited to, operating voltage, power dissipation, and operating temperature. 4. Oki assumes no responsibility or liability whatsoever for any failure or unusual or unexpected operation resulting from misuse, neglect, improper installation, repair, alteration or accident, improper handling, or unusual physical or electrical stress including, but not limited to, exposure to parameters beyond the specified maximum ratings or operation outside the specified operating range. 5. Neither indemnity against nor license of a third party's industrial and intellectual property right, etc. is granted by us in connection with the use of the product and/or the information and drawings contained herein. No responsibility is assumed by us for any infringement of a third party's right which may result from the use thereof. 6. The products listed in this document are intended for use in general electronics equipment for commercial applications (e.g., office automation, communication equipment, measurement equipment, consumer electronics, etc.). These products are not authorized for use in any system or application that requires special or enhanced quality and reliability characteristics nor in any system or application where the failure of such system or application may result in the loss or damage of property, or death or injury to humans. Such applications include, but are not limited to, traffic and automotive equipment, safety devices, aerospace equipment, nuclear power control, medical equipment, and life-support systems. 7. Certain products in this document may need government approval before they can be exported to particular countries. The purchaser assumes the responsibility of determining the legality of export of these products and will take appropriate and necessary steps at their own expense for these. 8. No part of the contents contained herein may be reprinted or reproduced without our prior permission. Copyright 2000 Oki Electric Industry Co., Ltd. 15/15 |
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